The technology described herein relates to data processing methods and apparatus in which sets of output data are to be generated by a data processing apparatus.
A data output to be generated by a data processing apparatus, e.g. a graphics output to be generated by a graphics processing system, is often generated as a sequence of plural sets of output data, e.g. plural frames of graphics data.
Each set of output data, e.g. frame, may be generated by a graphics processor of the system and then written to a so-called “frame buffer” in memory when it is ready for use, e.g. display. The frame buffer may then be read, e.g. by a display controller, and output, e.g. to a display (such as a screen or a printer), for use, e.g. for display.
Generating sets of output data often consumes a significant amount of processing power. Writing sets of output data to a frame buffer also often consumes a significant amount of processing power and memory bandwidth, particularly where, as is often the case, the frame buffer resides in a memory that is external to the graphics processor.
For example, in the case of a graphics output to be displayed, frames of graphics data may need to be generated and written to memory at a rate of 48 frames per second or higher, and each frame can require a significant amount of graphics data to be generated, particularly for higher resolution displays and high definition (HD) graphics.
In data processing apparatus, e.g. of portable devices, it is generally desirable to try to reduce the amount of processing resources needed to generate sets of output data, e.g. so as to reduce power consumption, increase processing speed and/or decrease memory bandwidth consumption, but without a corresponding undesirable reduction in the quality of the data output.
The Applicants believe that there remains scope for improvements to data processing methods and apparatus in which sets of output data are to be generated by a data processing apparatus.
The drawings show elements of a data processing apparatus that are relevant to embodiments of the technology described herein. As will be appreciated by those skilled in the art there may be other elements of the data processing apparatus that are not illustrated in the drawings. It should also be noted here that the drawings are only schematic, and that, for example, in practice the shown elements may share significant hardware circuits, even though they are shown schematically as separate elements in the drawings.